Evaluation of all wet PR Strip Clean by Using Single Wafer Clean Tool
对使用单晶圆清洗平台进行全湿法光阻去除工艺的评估
Steven Piao,Manager of Diffusion & Wet Clean Department, LTD, SMIC
超大规模CMOS制造技术发展到65nm及更高技术节点，LDD（轻掺杂漏区）结变得越来越窄。LDD区域中的杂质分布越来越靠近衬底表面。由于杂质丢失带来的表现将影响到器件的性能，LDD离子注入PR去除后工艺正变得越来越重要。灰化和后清洗工艺需要仔细的研究以在剂量损失和缺陷表现上取得满意的结果。因为O2等离子灰化（高能量）和湿槽工艺（高材料损失和低PRE）的本性使然，一些 LDD回路PR去除清洗的新方法开始被评估。在满足令人满意的COO和产能前提下，根据缺陷、材料损失、周期时间的减少等方面的表现，在单晶圆全湿法PR去除清洗工艺中评估结果表现良好，但器件性能的认证将要继续深入研究。
Speaker Bio.：
Steven Piao now is the
Manager of Diffusion & Wet Clean Department of LTD in SMIC. He takes the responsibility of FEOL single wafer clean evaluation、Ni strip clean process development for 65nm technology program、CT clean process development for 65nm technology program、NiPt strip clean process development for 65nm technology program、Implanted PR all strip wet clean for 65nm technology program、DUO clean process development for 90nm BEOL clean、Backside & bevel clean for de-Cu contamination process development、Low K & other Cu BEOL dielectric film wafer reclaim project、90nm & 65nm FEOL defect reduction and yield improvement project etc in SMIC. Before joined SMIC, Steven worked for HNS(Singapore)、Small Precision Tool 、China Huajing Microelectric Group for about 10 years total.
Abstract:
With CMOS manufacturing technology evolution arrival at 65nm and beyond, LDD (Lightly Doped Drain) junction is getting more and more shallow. Dopant distribution in LDD region is getting closer to substrate surface. Post LDD implant PR remove process is becoming critical as its behavior on dopant loss may impact device performance. Ash and post clean process need to carefully developed to get satisfactory result in both dose loss and defect performance. Due to the natural of O2 plasma ash (high energy) and wet bench process (high material loss and low PRE), some novel method for LDD loop PR strip clean is evaluated. Evaluation result shows good performance in single wafer all wet PR strip clean process in terms of defect performance, material loss, cycle time reduction with satisfactory COO and throughput. Device performance verification yet to be further studied.
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